NEWS
Free Institutional Consultancy Services
New Feature: Compare Your Institution with the Previous Year
Find a Professional: Explore Experts Across 197 Disciplines in 220 Countries!
Find a Professional
Print Your Certificate
New! Young University / Institution Rankings 2025
New! Art & Humanities Rankings 2025
New! Social Sciences and Humanities Rankings 2025
Highly Cited Researchers 2025
AD
Scientific Index 2025
Scientist Rankings
University Rankings
Subject Rankings
Country Rankings
login
Login
person_add
Register
insights
H-Index Rankings
insights
i10 Productivity Rankings
format_list_numbered
Citation Rankings
subject
University Subject Rankings
school
Young Universities
format_list_numbered
Top 100 Scientists
format_quote
Top 100 Institutions
format_quote
Compare & Choose
local_fire_department
Country Reports
person
Find a Professional
Donggang David Wu
Advanced Micro Devices, Inc - Santa Clara / United States
Others
AD Scientific Index ID: 4491865
-
Registration, Add Profile,
Premium Membership
Print Your Certificate
Ranking &
Analysis
Job
Experiences (0)
Education
Information (0)
Published Books (0)
Book Chapters (0)
Articles (0)
Presentations (0)
Lessons (0)
Projects (0)
Subject Leaders
Editorship, Referee &
Scientific Board (0 )
Patents /
Designs (0)
Academic Grants
& Awards (0)
Artistic
Activities (0)
Certificate / Course
/ Trainings (0)
Association &
Society Memberships (0)
Contact, Office
& Social Media
person_outline
Donggang David Wu's MOST POPULAR ARTICLES
1-)
Low-K sub spacer pocket formation for gate capacitance reductionS Luning, D Wu, K TranUS Patent 6,351,013, 20022302002
2-)
Formation of high-k gate dielectric layers for MOS devices fabricated on strained lattice semiconductor substrates with minimized stress relaxationB Yu, D WuUS Patent 6,784,101, 20041682004
3-)
Method of forming multiple fins for a semiconductor deviceZ Shi, D Wu, J Zhou, R LiUS Patent 8,003,466, 2011952011
4-)
Method of forming a semiconductor device with source/drain regions having a deep vertical junctionDD WuUS Patent 6,368,926, 2002652002
5-)
Control trimming of hard mask for sub-100 nanometer transistor gateM Aminpur, D Wu, S LuningUS Patent 6,482,726, 2002572002
ARTICLES
Add your articles
We use cookies to personalize our website and offer you a better experience. If you accept cookies, we can offer you special services.
Cookie Policy
Accept