Francesco Tesolin

Francesco Tesolin

Politecnico di Milano - Milano / Italy
Others
AD Scientific Index ID: 5955178
Polytechnic University of Milan
person_outline Francesco Tesolin's MOST POPULAR ARTICLES
1-) A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking …SM Dartizio, F Buccoleri, F Tesolin, L Avallone, A Santiccioli, A Iesurum, ...IEEE Journal of Solid-State Circuits 57 (12), 3538-3551, 2022212022
2-) A 12.9-to-15.1-GHz digital PLL based on a bang-bang phase detector with adaptively optimized noise shapingSM Dartizio, F Tesolin, M Mercandelli, A Santiccioli, A Shehata, S Karman, ...IEEE Journal of Solid-State Circuits 57 (6), 1723-1735, 2021222021
3-) 4.5 a 9.25 GHz digital PLL with fractional-spur cancellation based on a multi-DTC topologyG Castoro, SM Dartizio, F Tesolin, F Buccoleri, M Rossoni, D Cherniak, ...2023 IEEE International Solid-State Circuits Conference (ISSCC), 82-84, 2023212023
4-) 4.3 A 76.7 fs-lntegrated-Jitter and− 71.9 dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive DitheringSM Dartizio, F Tesolin, G Castoro, F Buccoleri, L Lanzoni, M Rossoni, ...2023 IEEE International Solid-State Circuits Conference (ISSCC), 3-5, 2023212023
5-) A 68.6fsrms-total-integrated-jitter and 1.56μs-locking-time fractional-N bang-bang PLL based on type-II gear shifting and adaptive frequency switchingSM Dartizio, F Buccoleri, F Tesolin, L Avallone, A Santiccioli, A Iesurum, ...2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 1-3, 2022212022