Hiroki Matsutani

Hiroki Matsutani

Keio University - Tokyo / Japan
Engineering & Technology / Computer Science
AD Scientific Index ID: 393166
慶應義塾大学
person_outline Hiroki Matsutani's MOST POPULAR ARTICLES
1-) A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interfaceN Miura, Y Koizumi, E Sasaki, Y Take, H Matsutani, T Kuroda, H Amano, ...2013 IEEE COOL Chips XVI, 1-3, 20131882013
2-) A case for random shortcut topologies for HPC interconnectsM Koibuchi, H Matsutani, H Amano, DF Hsu, H CasanovaACM Sigarch Computer Architecture News 40 (3), 177-188, 20121872012
3-) A lightweight fault-tolerant mechanism for network-on-chipM Koibuchi, H Matsutani, H Amano, TM PinkstonSecond ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008), 13-22, 20081792008
4-) Prediction router: Yet another low latency on-chip router architectureH Matsutani, M Koibuchi, H Amano, T Yoshinaga2009 IEEE 15th International Symposium on High Performance Computer …, 20091352009
5-) Run-time power gating of on-chip routers using look-ahead routingH Matsutani, M Koibuchi, H Amano, D Wang2008 Asia and South Pacific Design Automation Conference, 55-60, 20081332008