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José A Tierno
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José A Tierno's MOST POPULAR ARTICLES
1-)
A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neuronsJ Seo, B Brezzo, Y Liu, BD Parker, SK Esser, RK Montoye, B Rajendran, ...2011 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 20114142011
2-)
A wide power supply range, wide tuning range, all static CMOS all digital PLL in 65 nm SOIJA Tierno, AV Rylyakov, DJ FriedmanIEEE Journal of Solid-State Circuits 43 (1), 42-51, 20082312008
3-)
Active management of timing guardband to save energy in POWER7CR Lefurgy, AJ Drake, MS Floyd, MS Allen-Ware, B Brock, JA Tierno, ...proceedings of the 44th Annual IEEE/ACM International Symposium on …, 20111912011
4-)
Integrated transversal equalizers in high-speed fiber-optic systemsH Wu, JA Tierno, P Pepeljugoski, J Schaub, S Gowda, JA Kash, A HajimiriIEEE Journal of Solid-State Circuits 38 (12), 2131-2137, 20032002003
5-)
Introducing the adaptive energy management features of the power7 chipM Floyd, M Allen-Ware, K Rajamani, B Brock, C Lefurgy, AJ Drake, ...IEEE Micro 31 (2), 60-75, 20111452011
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