L Entrena

L Entrena

Universidad Carlos III de Madrid - Getafe / Spain
Engineering & Technology / Electrical & Electronic Engineering
AD Scientific Index ID: 1244267
Carlos III University of Madrid
person_outline L Entrena's MOST POPULAR ARTICLES
1-) Autonomous fault emulation: A new FPGA-based acceleration system for hardness evaluationC Lopez-Ongil, M Garcia-Valderas, M Portela-Garcia, L EntrenaIEEE Transactions on Nuclear Science 54 (1), 252-261, 20071632007
2-) Combinational and sequential logic optimization by redundancy addition and removalLA Entrena, KT ChengIEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 19951501995
3-) Soft error sensitivity evaluation of microprocessors by multilevel emulation-based fault injectionL Entrena, M Garcia-Valderas, R Fernandez-Cardenal, A Lindoso, ...IEEE Transactions on Computers 61 (3), 313-322, 20101372010
4-) Multi-level logic optimization by redundancy addition and removalKT Cheng, LA Entrena1993 European Conference on Design Automation with the European Event in …, 19931321993
5-) Sequential logic optimization by redundancy addition and removalL Entrena, KT ChengProceedings of 1993 International Conference on Computer Aided Design (ICCAD …, 19931221993