Loïc Gaben,

Soitec - / France

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AD Scientific Index ID: 5085743

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Loïc Gaben,'s MOST POPULAR ARTICLES

1-) Vertically stacked-nanowires MOSFETs in a replacement metal gate process with inner spacer and SiGe source/drainS Barraud, V Lapras, MP Samson, L Gaben, L Grenouillet, ...2016 IEEE International Electron Devices Meeting (IEDM), 17.6. 1-17.6. 4, 20161182016

2-) Dual-channel CMOS co-integration with Si NFET and strained-SiGe PFET in nanowire device architecture featuring sub-15nm gate lengthP Nguyen, S Barraud, C Tabone, L Gaben, M Cassé, F Glowacki, ...2014 IEEE International Electron Devices Meeting, 16.2. 1-16.2. 4, 2014342014

3-) Opportunities and challenges of nanowire-based CMOS technologiesS Barraud, M Cassé, L Gaben, P Nguyen, JM Hartmann, MP Samson, ...2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference …, 2015222015

4-) Evaluation of Stacked Nanowires Transistors for CMOS: Performance and Technology OpportunitiesL Gaben, S Barraud, MP Samson, MA Jaud, S Martinie, O Rozeau, ...ECS Transactions 72 (4), 43-54, 2016

5-) Stacked-Nanowire and FinFET transistors: guidelines for the 7nm nodeL Gaben, S Barraud, MA Jaud, S Martinie, O Rozeau, J Lacord, G Hiblot, ...Proc. Int. Conf. Solid State Devices Mater.(SSDM), 1006-1007, 2015

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