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Naveen John
Synopsys Inc - Mountain View / United States
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AD Scientific Index ID: 5512455
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Naveen John's MOST POPULAR ARTICLES
1-)
A unified clock and switched-capacitor-based power delivery architecture for variation tolerance in low-voltage SoC domainsF ur Rahman, S Kim, N John, R Kumar, X Li, R Pamula, KA Bowman, ...IEEE Journal of Solid-State Circuits 54 (4), 1173-1184, 2019262019
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A combined all-digital PLL-buck slack regulation system with autonomous CCM/DCM transition control and 82% average voltage-margin reduction in a 0.6-to-1.0 V cortex-M0 processorX Sun, S Kim, F ur Rahman, VR Pamula, X Li, N John, VS Sathe2018 IEEE International Solid-State Circuits Conference-(ISSCC), 302-304, 2018152018
3-)
An All-Digital Fused PLL-Buck Architecture for 82% Average Vdd-Margin Reduction in a 0.6-to-1.0-V Cortex-M0 ProcessorX Sun, F ur Rahman, VR Pamula, S Kim, X Li, N John, VS SatheIEEE Journal of Solid-State Circuits 54 (11), 3215-3225, 2019142019
4-)
An all-digital unified clock frequency and switched-capacitor voltage regulator for variation tolerance in a sub-threshold ARM cortex M0 processorFU Rahman, S Kim, N John, R Kumar, X Li, R Pamula, KA Bowman, ...2018 IEEE Symposium on VLSI Circuits, 65-66, 2018142018
5-)
Electrical circuit design using cells with metal linesRB Lefferts, J Naveen, LJH Alves, J Amanda, N Gopalan, ...US Patent 11,334,705, 202232022
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